1. Field of Application
The present invention relates to a control signal generating circuit and to a method of using the control signal generating circuit. In particular, the invention relates to a control signal generating circuit which generates a clock signal based on applying frequency multiplication or frequency division to a reference signal, and to a method of using such a circuit.
2. Description of Related Technology
A type of PLL (phase locked loop) circuit is known (for example as described in Japanese Patent First Publication No. 7-183800, referred to in the following as reference document 1) whereby a reference signal is frequency-stabilized by being generated using a quartz crystal vibrator and wherein periods of the reference signal are counted by using a high-frequency clock signal having a frequency that is sufficiently higher than that of the reference signal. The resultant count value is used to derive a clock signal through multiplying or dividing the period of the reference signal.
An example of such a PLL circuit is shown in FIG. 8. Here, the clock signal generating circuit 101 includes a pulse delay circuit 110, a period measurement section 120, a control section 130 and an output section 140. The pulse delay circuit 110 is made up of a plurality of delay elements DU connected in a ring configuration, around which a pulse signal successively circulates, being sequentially delayed by the delay elements. The period measurement section 120 generates period data D expressing the value of period of a reference signal CKI by determining the number of delay elements DU that are traversed by the pulse signal during each interval between a rising edge of the clock signal CKI and a succeeding rising edge, and converting the number to a binary digital value. This is done based on traversal signals P1˜Pm which are successively outputted from the respective delay elements DU of is the pulse delay circuit 110, (where “traversal signals” signifies successive outputs of the pulse signal from respective delay elements).
The control section 130 generates control data CD expressing a required value of period of a clock signal CKO that is to be generated. This is done by multiplying or dividing the period data DT from the period measurement section 120 by a set value MN. The output section 140 operates based on the control data CD and on the traversal signals P1˜Pm, to generate the clock signal CKO with a period that is equal to the period of the reference signal CKI multiplied by the set value MN.
However as illustrated in FIG. 9, with this prior art example, it is necessary that the phase of the clock signal CKO be locked to the phase of the reference signal CKI. That is to say, the phase difference Tdef(k) (where k=1, 2, . . . ) between each rising edge of a specific one of the clock signal CKO and reference signal CKI and the succeeding rising edge of the other one of these signals is made equal to zero, where the specific signal is the one of the clock signal CKO and reference signal CKI having the lower frequency of the two signals.
Hence it is necessary that each possible frequency value which can be set as the frequency of the clock signal CKO must be equal to the frequency of the reference signal CKI multiplied by an integer, or multiplied by 1 divided by an integer. That is to say, the set value MN is restricted to being an integer, or 1 divided by an integer. Hence, the number of possible frequencies that can be set for the clock signal CKO (by using a single reference signal frequency) is substantially limited, which is a severe design restriction. More specifically, a single reference signal frequency cannot be used for selectively generating an arbitrary one of a plurality of clock signals that successively differ in frequency by only a small amount.
Thus, when it is necessary that the clock signal CKO can be generated at any of a plurality of respectively different frequencies, it may not be possible to obtain all of these clock signal frequencies through multiplying the frequency of the reference signal CKI by an integer or by 1 divided by an integer. Hence in such a case it becomes necessary to use a plurality of reference signals CKI having respectively different frequencies, in order to be able to generate the clock signal CKO at all of the required frequencies.